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1 tm cdp1851, cdp1851c cmos programmable i/o interface description the cdp1851 and cdp1851c are cmos programmable two- port i/os designed for use as general-purpose i/o devices. they are directly compatible with cdp1800-series micropro- cessors functioning at maximum clock frequency. each port can be programmed in either byte-i/o or bit-programmable modes for interfacing with peripheral devices such as printers and keyboards. both ports a and b can be separately programmed to be 8-bit input or output ports with handshaking control lines, rdy and strobe. only port a can be programmed to be a bidirectional port. this configuration provides a means for communicating with a peripheral device or microprocessor system on a single 8-bit bus for both transmitting and receiving data. handshaking signals are provided to maintain proper bus access control. port a handshaking lines are used for input control and port b handshaking lines are used for output; therefore port b must be in the bit-programmable mode where handshaking is not used. ports a and b can be separately bit programmed so that each individual line can be designated as an input or output line. the handshaking lines may also be individually programmed as input or output when port a is not in bidirectional mode. the cdp1851 has a supply-voltage range of 4v to 10.5v, and the cdp1851c has a range of 4v to 6.5v. both types are sup- plied in 40-lead dual-in-line plastic (e suffix) or hermetic ceramic (d suffix) packages. the cdp1851c is also available in chip form (h suffix). features ? 20 programmable i/o lines programmable for operation in four modes: - input - output - bidirectional - bit-programmable operates in either i/o or memory space ordering information package temp. range 5v 10v pkg. no. pdip -40 o c to +85 o c CDP1851CE cdp1851e e40.6 burn-in CDP1851CEx - e40.6 sbdip -40 o c to +85 o c cdp1851cd - d40.6 burn-in cdp1851cdx cdp1851dx d40.6 march 1997 file number 1056.2 pinout cdp1851, cdp1851c (pdip, sbdip) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 clock cs ra0 ra1 bus0 bus1 bus2 bus3 bus4 bus5 bus6 bus7 clear a int b int b rdy b b0 b1 v ss 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd rd/we wr/re tpb a rdy a a0 a1 a2 a3 a4 a5 a6 a7 b7 b6 b5 b4 b3 b2 strob e strobe cdp1851 programming modes mode (8) port a data pins (2) port a handshaking pins (8) port b data pins (2) port b handshaking pins input accept input data ready, strobe accept input data ready, strobe output output data ready, strobe output data ready, strobe bidirectional (port a only) transfer in- put/output data input handshaking for port a must be previous- ly set to bit-pro- grammable mode output handshaking for port a bit-program- mable programmed in- dividually as in- puts or outputs programmed individ- ually as inputs or out- puts programmed indi- vidually as inputs or outputs programmed individ- ually as inputs or out- puts caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 functional diagram absolute maximum ratings thermal information dc supply-voltage range, (v dd ) (voltage referenced to v ss terminal) cdp1851 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to+11v cdp1851c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7v input voltage range, all inputs . . . . . . . . . . . . . . -0.5 to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma device dissipation per output transistor for t a = full package-temperature range (all package type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mw operating-temperature range (t a ) package type d, h . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c package type e . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 50 n/a sbdip package. . . . . . . . . . . . . . . . . . 36 12 maximum storage temperature range (t stg ). . . . -65 o c to +150 o c maximum lead temperature (during soldering) at distance 1/16 1/32 inch (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indica ted in the operational sections of this specification is not i mplied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. operating conditions at t a = full package-temperature range. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges: parameter limits units cdp1851 cdp1851c min max min max dc operating voltage range 4 10.5 4 6.5 v input voltage range v ss v dd v ss v dd v mode control and status registers b0 b1 b2 b3 b4 b5 b6 b7 ready strobe section b a0 a1 a2 a3 a4 a5 a6 a7 ready strobe section a clock cs ra0 ra1 wr/rd rd/wr tpb clear address decode and read/ write logic a int b int interrupt masking and logic data bus buffer data bus figure 1. functional diagram for cdp1851 and cdp1851c cdp1851, cdp1851c
3 functional description the cdp1851 has four modes of operation: input, output, bidirectional, and bit-programmable. port a is programmable in all modes; port b is programmable in all but the bidirectional mode. a control byte must be loaded into the control register to program the ports. in the input and output modes, each port has two handshaking signals, strobe and rdy. in the bidirectional mode, port a has four handshaking signals: a rdy and a strobe for input, b rdy and b strobe for output. if port a is programmed in the bidirectional mode, port b must be programmed in the bit-programmable mode. each terminal of port a or b may be individually programmed for input or output in the bit- programmable mode. since handshaking is not used in this mode, the rdy and strobe lines may also be used for bit- programming if port a is not in the bidirectional mode. input mode when a peripheral device has data to input, it sends a strobe pulse to the plo. the leading edge of this pulse clears the rdy line, inhibiting further transmission from the peripheral. the trailing edge of the strobe pulse latches the data into the plo buffer register and also activates the int line to signal the cpu to read this data. the lnt pin can be wired static electrical specifications at t a = -40 o c to +85 o c, v dd 5%, unless otherwise specified parameter conditions limits units v o (v) v in (v) v dd (v) cdp1851 cdp1851c min (note1) typ max min (note1) typ max quiescent device current i dd - 0, 5 5 - 0.01 50 - 0.02 200 a - 0, 10 10 - 1 200 - - - a output low drive (sink) current i ol 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - ma 0.5 0, 10 10 2.6 5.2 - - - - ma output high drive (source) current i oh 4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - ma 9.5 0, 10 10 -2.6 -5.2 - - - - ma output voltage low-level (note 2) v ol - 0, 5 5 - 0 0.1 - 0 0.1 v - 0, 10 10 - 0 0.1 - - - v output voltage high level (note 2) v oh -0, 554.9 5 - 4.9 5 - v - 0, 10 10 9.9 10 - - - - v input low voltage v il 0.5, 4.5 -5- - 1.5- - 1.5v 0.5, 9.5 -10--3---v input high voltage v lh 0.5, 4.5 -53.5 - -3.5 - - v 0.5, 9.5 -107-----v input leakage current i ln any input 0, 5 5 - - 1- - 1 a 0, 10 10 - - 2--- a three-state output leakage current i out 0, 5 0, 5 5 - - 1- - 1 a 0, 10 0, 10 10 - - 1--- a operating current (note 3) i dd1 - 0, 5 5 - 1.5 3 - 1.5 3 ma - 0, 10 10 - 6 12 - - - ma input capacitance c in ---- 5 7.5- 5 7.5pf output capacitance c out - - - - 10 15 - 10 15 pf notes: 1. typical values are for t a = 25 o c and nominal v dd . 2. i ol = i oh = 1 a 3. operating current is measured at 200khz for v dd = 5v and 400khz for v dd = 10v, with open output (worst-case frequencies for cdp1802a system operating at maximum speed of 3.2mhz). cdp1851, cdp1851c
4 to the int pin of the cpu or the ef lines for polling. the cpu then executes an input or a load instruction, depending on the mapping technique used. in either case the proper code must be asserted on the rao, ra1, and cs lines to read the buffer register (see table 6). the int line is deactivated on the leading edge of tpb. the trailing edge of tpb sets the rdy line to signal the periph- eral that the port is ready to be loaded with new data. if rdy is low when the input mode is entered (i.e. after a reset), a ?dummy? read must be done to set rdy high and signal the peripheral device that the port is ready to be loaded. output mode a peripheral strobe pulse sent to the plo generates an interrupt to signal the cpu that the peripheral device is ready for data. the cpu executes the proper output or store instruction. data are then read from memory and placed on the bus. the data are latched into the port buffer at the end of the window when re/we = 0 and wr/re = 1. the rdy line is also set at this time, indicating to the peripheral that there is data in the port buffer. the int line is deactivated at the beginning of the window. after the peripheral reads valid port data, it can send another strobe pulse, clearing the rdy line and activating the int line as in the input mode. bidirectional mode this mode programs port a to function as both an input and output port. the bidirectional feature allows the peripheral to control port direction by using both sets of handshake signals. the port a handshaking pins are used to control input data from peripheral to plo, whil e the port b handshaking pins are used to control output data from plo to peripheral. data are transferred in the same manner as the input and output modes. since a int is used for both input and output, the sta- tus register must be read to determine what condition caused a int to be activated (see table 5). bit-programmable mode this mode allows individual bits of port a or port b to be programmed as inputs or outputs. to output data to bits programmed as outputs, the cpu loads a data byte into the 8-bit port as in the output mode (no handshaking). only bits programmed for outputs latch this data. data must be stable when reading from bits programmed as inputs, since the input bits do not latch. when the cdp1851 inputs data to the cpu the cpu also reads the output bits latched during the last output cycle. the rdy and strobe lines may be used for i/o by using the strobe/rdy i/o control byte in table 2. an additional feature available in the bit-programmable mode is the ability to generate interrupts based on input/output byte combinations. these interrupts can be programmed to occur on logic conditions (and, or, nand, and nor) generated by the eight i/o lines of each port (the strobe and rdy lines cannot generate interrupts). a0 a1 a2 a3 a4 a5 a6 a7 int bus 0-7 cdp1800 family p tpa mwr mrd tpb v dd 10k ? ra0 ra1 a rdy port a0 - a7 port b0 - b7 a int bus 0-7 pio no. 1 clock rd/we wr/re tpb cdp1851 b int cs b rdy a strobe b strobe ra0 ra1 a rdy port a0 - a7 port b0 - b7 pio no. 2 clock rd/we wr/re tpb cdp1851 b rdy a strobe b strobe cs a int b int address register address selects 8001 no. 1 control/status reg 8002 no. 1 port a 8003 no. 1 port b 8004 no. 2 control/status reg 8008 no. 2 port a 800c no. 2 port b figure 2. memory space i/o. this config uration allows up to four cdp1851s to o ccupy memory space 8xxx wit h no additional hardware (a4-a5 and a6-a7 are used as ra0 and ra1 on the third and fourth pio?s) cdp1851, cdp1851c
5 programming initialization and controls the cdp1851 plo must be cleared by a low on the clear input during power-on to set it for programming. once programmed, modes can be changed without clearing except when exiting the bit-programmable mode. a low on the clear input sets both ports to the input modes, disables interrupts, unmasks all bit-programmed interrupt bits, and resets the status register, a rdy, and b rdy. mode setting the control register must be sequentially loaded with the appropriate mode set control bytes in order as shown in table 1 (i.e. input mode then output mode, etc.). port a is set with the set a bit = 1 and port b is set with the set b bit = 1. if a port is set to the bit-programmable mode, the bit-programming control byte from table 2 must be loaded. a bit is programmed for output with the i/o bit = 1 and for input with the i/o bit = 0. the strobe and rdy lines may be programmed for input or output with the strobe/rdy control byte of table 2. input data on the strobe and rdy lines is detected by reading the status register. when using the strobe or rdy lines for output, the control byte must be loaded every time output data is to be changed. to program logical conditions that will gen- erate an interrupt, the interrupt control byte of table 3 must be loaded. an interrupt mask of the eight i/o lines may be loaded next, if bit d4 (mask follows) of the interrupt control byte = 1. the i/o lines are masked if the corresponding bit of the inter- rupt mask register is 1, otherw ise it is monitored. any combi- nation of masked bits are permissible, except all bits masked (mask = ff). int enable disable to enable or disable the int line in all modes, the interrupt enable/disable byte must be loaded (see table 4). inter- rupts can also be detected by reading the status register (see table 5). all interrupts should be disabled when programming or false interrupts may occur. the int outputs are open drain nmos devices that allow wired o ring (use 10k pull-up registers). set ports a and b to input, output, or bit-programmable mode using table 1 generate clear pulse at pin 13 is either port set to the bit-programmable mode 3 no yes now set port a to bidirectional mode, if desired set master interrupt enable/disable using table 4 main program will interrupts be used for bit-programmed port? perform following sequence before programming port a to bidirectional mode set bit direction using table 2 set bit logical conditions and masking using table 3 repeat for each bit-programmable port repeat for each bit-programmable port yes no figure 3. a flow chart guide to cdp1851 mode programming n otes: 1. strobe/ready i/o control byte (table 2) is also used to output data to strobe and ready lines when bit-programmed. 2. status register (table 2) is used to input dat a from strobe and ready lines when bit-programmed. 3. interrupt status is also read from status register. cdp1851, cdp1851c
6 table 1. (ra1 = 0, ra0 = 1) (note 1) mode set 76543210 input 0 0 x set b set a x 1 1 output 0 1 x set b set a x 1 1 bit-programmable 1 1 x set b set a x 1 1 bidirectional 1 0 x x set a x 1 1 note: 1. modes should be set in order as shown in table 1. if either port is set for bit-progr ammable mode, the two following control bytes should immediately follow: table 2. (ra1 = 0, ra0 = 1) 76543210 bit-programming (note 1) i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 strobe/rdy i/o control (notes 2 - 8) d7 d6 d5 d4 d3 d2 d1 d0 notes: 1. output = 1, input = 0 2. (d1) 0 = port a, 1 = port b 3. (d2) 0 = no change to rdy line function, 1 = change per bit (d6) 4. (d3) 0 = no change to strobe line function, 1 = change per bit (d7) 5. (d4) rdy line output data 6. (d5) strobe line output data 7. (d6) rdy line used as: output = 1 input = 0 8. (d7) strobe line used as: output = 1 input = 0 if interrupts will be used for either bit-programmed port, the following control bytes should be loaded. table 3. (ra1 = 0, ra0 = 1) interrupt control 76543210 logical conditions and mask 0 d6 d5 d4 d3 1 0 1 notes: 1. (d3) 0 = port a, 1 = port b 2. (d4) 0 = no change in mask, 1 = mask follows (see table 3a) 3. (d5)(d6) 0, 0 = nand; 1, 0 = or; 0, 1 = nor; 1, 1 = and table 3a. (ra1 = 0, ra0 = 1) interrupt control 76543210 mask register (if d4 = 1) b7 mask b6 mask b5 mask b4 mask b3 mask b2 mask b1 mask b0 mask note: 1. if bn mask = 1 then mask bit (for n = 0 to 7) cdp1851, cdp1851c
7 table 4. (ra1 = 0, ra0 = 1) interrupt control 76543210 interrupt enable/disable int enable xxxa/b0 0 1 notes: 1. int enable = 1, int enabled = 0, int disabled 2. a/b = 0, port a = 1, port b table 5. (ra1 = 0, ra0 = 1) 76543210 status register d7 d6 d5 d4 d3 d2 d1 d0 notes: 1. all modes (d0) b int status (1 means set) (d1) a int status (1 means set) 2. bidirectional mode only (d2) 1 = a int was caused by a strobe (d3) 1 = a int was caused by b strobe 3. bit-programmable mode (d4) a rdy input data (d5) a strobe input data (d6) b rdy input data (d7) b strobe input data table 6. cpu controls (note 1) cs ra1 ra0 rd/we wr/re action 0xxxxno-op bus three-stated x 0 0 x x no-op bus three-stated x x x 0 0 no-op bus three-stated x x x 1 1 no-op bus three-stated x x x 1 1 no-op bus three-stated 10110r ead status register (note 1) 10101 load control register 11010r ead port a (note 1) 11001 load port a 11110r ead port b (note 1) 11101 load port b note: 1. read = rd/we = 1 and wr/re = 0 is latched on trailing edge of clock. table 7. memory i/o use rd/we input wr/re input tpb input } pio terminal i/o space mrd tpb tpb } cpu terminals memory space mwr mrd tpb cdp1851, cdp1851c
8 function pin definition clock (input): positive input pulse that latches read and cs on its trailing edge. cs - chip select (input) a high-level voltage at this input selects the cdp1851 plo. ra0 - register address 0 (input): this input and ra1 are used to select either the ports or the control/status registers. ra1 - register address 1(input): see rao bus 0 - bus 7: bidirectional cpu data bus. clear (input) a low-level voltage at this input resets both ports to the input mode, and also resets the status register, a rdy, b rdy, and interrupt enable (disabling interrupts). a int - a interrupt (output): a low-level voltage at this output indicates the presence of one of the interrupt conditions listed in table 3. this output is an open-drain nmos device (to allow wired o ring) and must be tied to a pullup resistor, normally 10k ? . b int - b interrupt (output): a low-level voltage at this output indicates the presence of one of the interrupt conditions listed in table 3. this output is also an open-drain nmos device and must be tied to a pullup resistor. b rdy - b ready (output): this output is a handshaking or data bit i/o line in the bit- programmable mode. b strobe (input): an input handshaking line for port b in the input and output modes, and for port a when it is in the bidirectional mode. it can be used as a data bit i/o line in the bit-programmable mode except when port a is not programmed as bidirectional. b0 - b7: data input or output lines for port b. v ss ground a0 - a7: data input or output lines for port a. a strobe (input): an input handshaking line for port a in the input, output, and bidirectional modes. it can also be used as a data bit i/o line when port a is in the bit-programmable mode. ardy - aready (output): a output handshaking line or data bit i/o line. tpb (input): a positive input pulse used as a data load, set, or reset strobe. wr/re - write/read enable (input): a positive input used to write data from the cdp1851 to the cpu bus. rd/we - read/write enable (input): a positive input used to read data from the cpu bus to the cdp1851 bus. v dd : positive supply voltage. cdp1851, cdp1851c
9 mrd tpb int bus 0-7 cdp1802 tpa n2 n1 n0 v dd 10k ? rd/we wr/re a rdy port a0 - a7 port b0 - b7 a int bus 0-7 clock cs ra1 ra0 cdp1851 b int b rdy a strobe b strobe rd/we wr/re a rdy port a0 - a7 port b0 - b7 clock cs ra1 ra0 cdp1851 b rdy a strobe b strobe tpb a int b int tpb bus 0-7 figure 4. i/o space i/o cdp1851, cdp1851c
10 dynamic electrical specifications at t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf parameter v dd (v) limits units cdp1851 cdp1851c min (note 1) typ (note 2) max min (note 1) typ (note 2) max input mode see figures 4 and 5 minimum setup times: chip select to clock t cscl 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns rd/we to clock t rwcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns wr/re to clock t wrcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns data in to strobe t dlst 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns minimum hold times: chip select after clock t hcscl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns address after tpb t hatpb 5- -50 0 - -50 0 ns 10 - -25 0 - - - ns data in after strobe t hstdl 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns data bus out after address t hadoh 5 50 325 500 50 325 500 ns 10 25 165 250 - - - ns propagation delay times: tpb to int t pint 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns strobe to int t stlnt 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns tpb to rdy t tprdy 5 - 250 375 - 250 375 ns 10 - 125 200 - - - ns strobe to rdy t strdy 5 - 260 400 - 260 400 ns 10 - 130 200 - - - ns minimum pulse widths: clock t wcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns tpb t wtpb 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns strobe t wst 5 - 100 150 - 100 150 ns 10 - 50 75 - - - ns access time, address to data bus out t ada 5 - 325 500 - 325 500 ns 10 - 165 250 - - - ns notes: 1. typical values are for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. cdp1851, cdp1851c
11 test circuit and waveforms figure 5. interrupt signal propagation delay time test circuit and waveforms figure 6. input mode timing waveforms a 1k ? b 1k ? 50pf 50pf a int b int cdp1851 50% 50% 10% 50% t stint t pint t wint input signal a, b v dd t hadoh t hatpb t ada valid port address io or ii data bus ra1/ra0 wr/re = (tpb) rd/we = (mrd ) i/o space rd/we = (mwr ) wr/re = (mrd ) memory space cs clock = (tpa) tpb data-in strobe int rdy t strdy t wst t stint t dist t hstdi t pint t tprdy t wtpb t wcl t cscl t hcscl t wrcl t rwcl cdp1851, cdp1851c
12 dynamic electrical specifications at t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf parameters v dd (v) limits units cdp1851 cdp1851c min (note 1) typ (note 2) max min (note 1) typ (note 2) max output mode see figures 4 and 6 minimum setup times: chip select to clock t cscl 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns rd/we to clock t rwcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns wr/re to clock t wrcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns address to write (note 3) t aw 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns data bus to write (note 3) t dw 5 - 80 120 - 80 120 ns 10 - 40 60 - - - ns minimum hold times: chip select after clock t hcscl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns address after write (note 3) t haw 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns data bus after write (note 3) t hdw 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns propagation delay times: write to data out (note 3) t wdo 5 - 225 350 - 225 350 ns 10 - 125 200 - - - ns write to int (note 3) t wint 5 - 300 450 - 300 450 ns 10 - 150 225 - - - ns write to rdy (note 3) t wrdy 5 - 350 525 - 350 525 ns 10 - 175 275 - - - ns strobe to lnt t stlnt 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns strobe to rdy t strdy 5 - 260 400 - 260 400 ns 10 - 130 200 - - - ns minimum pulse widths: clock t wcl 5 - 75 120 - 75 120 ns 10 - 40 60 - - - ns strobe t wst 5 - 100 150 - 100 150 ns 10 - 50 75 - - - ns write (note 3) t ww 5 - 175 275 - 175 275 ns 10 - 90 150 - - - ns notes: 1. typical values are for t a = 25 o c and nominal voltages. 2. maximum limits of minimum characteristics are the values above which all devices function. 3. write is the overlap of rd/we = 0 and wr/re = 1. cdp1851, cdp1851c
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com data bus ra1/ra0 rd/we = (mrd ) wr/we = (tpb) i/o space rd/we = (mwr ) wr/re = (mrd ) memory space cs clock = (tpa) data-out strobe rdy int t wint t wtpb t wrdy t wst t strdy t stint valid data out t wcl t hcscl t cscl t wrcl t wdo t ww (note 1) t rwcl t aw t haw valid port address io or ii valid data t dw t dw n ote: 1. write is the overlap of wr/re = 1 and rd/we = 0 figure 7. output mode timing waveforms cdp1851, cdp1851c

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